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Verilog: Modeling, Simulation and Synthesis
Homework #1
1. a. Write a Verilog structural model for 3x8 binary decoder. Use the following module header:
module ThreexEight ( . );
output .;
input..;
o o o
endmodule
Write a well documented exhaustive testbench to test the 3x8 binary decoder of part a.
module ThreexEight(f, i, enable);
output [7:0] f;
input [2:0] i;
input enable;
Generate the displayed output, in the right order, for the following Verilog code. Indicate which system task is responsible for what output.
module display_example;
reg [15:0] data1, data2;
reg index;
initial
begin
$writeo (%d , $time, , %h \t, data1, , %h \t, data1, , index, \n);
#31 data1=15 ; data2 = 10; index = 1;
$displayh ($time, , data1, , data2, , index);
end
initial
begin
#5 data2 = 31 ; index = 0;
$strobe ($time , , data2 , , index);
$display ($time , , data2 , , index);
data2 = 15;
end
endmodule
Complete the following table for the above circuit:
4. a. Write a structural model of a 4-input multiplexer by instantiating the 2-input mux of Lab #1: MUX2_1(out, a, b, sel). Use the following module header:
module MUX4_1(out, In, sel);
output out;
input [3:0] In ;
input [1:0] sel;
o o o
endmodule
Write a well documented exhaustive testbench to test the 4-input multiplexer of part a. Use hierarchical referencing to monitor every intermediate signal along the path from In[0] to the output.
5. a. Using nand and xor Verilog primitives only, construct a full-adder module assuming the following:
nand gates have a time delay of 10 ns each, and
xor gates have a time delay of 15 ns each.
Use the following module header:
module Full_adder ( cout, Sum, X, Y, cin);
output cout;
output Sum;
input X, Y ;
input cin;
o o o
endmodule
b. Write a structural model of a 4-bit adder by instantiating the full adder module of part a (use an array of instances if possible). Use the following module header:
module Adder_4( cout, Sum, X, Y, cin);
output cout;
output [3:0] Sum;
input [3:0] X, Y ;
input cin;
o o o
endmodule
Write a testbench to test the 4-bit adder of part b. Use hierarchical referencing to monitor every intermediate signal along the path from X[2] to the output Sum[3].
6. Are each of the following legal Verilog statement? If not, identify the error and suggest a correction for it.
a. 'timescale 1ns/1ns
b. `timescale 50 ns / 10 ns;
c. `timescale 100 ms /1 ns
d. `timescale 1ns
e. `timescale 1ns/100ps
module One (...);
o o o
endmodule
`timescale 10ns/1ns
module Two (...);
o o o
endmodule
` timescale 100fs/1ns
g. ` t i m e s c a l e 1 0 0 n s / 1 0 n s
h. `timecsale 10ns/1ns
i. `timescale 100 ns / 10 ns
j. `timescale 100ms/10ms
k. `timescale 100s/10s
l. `timescale 10ns/1ns
o o o
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